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PRELIMINARY
Z86217/C17 CP95KEY1000
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
Z86217/C17
CMOS Z8(R) 8-BIT MICROCONTROLLERS (POINTING DEVICE/TRACKBALL)
FEATURES
Part Number Z86217 Z86C17
* General-Purpose
ROM (Kbytes) 2 2
RAM* (Bytes) 124 124
I/O Lines 14 14
Speed (MHz) 4 4
s s s s s s s
Permanent Watch-Dog Timer (WDT) Oscillator Filter Two Programmable 8-Bit Counter/Timers Low-EMI Operation Scalable Trip-Point Buffer On-Board Pull-Up Resistors High Drive Ports Can Sink 20 mA Per Pin, with Three Pins Maximum
s s s
18-Pin DIP and SOIC Packages 3.0- to 5.5-Volt Operating Range 0C to 70C Operating Temperature Range
GENERAL DESCRIPTION
The Z86217/C17 are members of Zilog's Z8(R) family of microcontrollers designed to reduce external system components and offer easy software/hardware development tools for pointing device and trackball applications. The devices feature on-board pull-up resistors, and a scalable trip-point buffer to accommodate opto-transistor outputs. The high drive ports are capable of up to 20 mA (at VOL = 0.8-volt) current sinking per pin, with three pins maximum, providing extra sinking current capability. The Z86217/C17's permanently enabled Watch-Dog Timer (WDT) operates upon power-up of the MCU, and provides added operational reliability for pointing device and trackball environments. An oscillator filter assists in separating out high-frequency noise from the oscillator input pin. Two on-chip counter/timers with a large number of selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications.
Notes: Refer to the DC electrical characteristics for detailed specification of the sinking current. On the Z86C17, P24-P27 has a 20K pull-up, and P32 has a 47K pulldown. The Z86217 does not have these functions. All Signals with a preceding front slash, "/", are active Low, e.g.; B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
CP95KEY1000 8/95
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PRELIMINARY
Z86217/C17 CP95KEY1000
XTAL
BLOCK DIAGRAM
Input VDD VSS
Port 3
Machine Timing & Inst. Control
ALU Counter/ Timers (2) Prg. Memory 2048 x 8-Bit
FLAG
Interrupt Control
Register Pointer Register File 144 x 8-Bit
Program Counter
Port 2
Port 0
I/O (Bit Programmable)
I/O
Functional Block Diagram
PIN DESCRIPTIONS
P24 P25 P26 P27 VDD XTAL2 XTAL1 P31 P32
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
P23 P22 P21 P20 VSS P02 P01 P00 P33
P24 P25 P26 P27 VDD XTAL2 XTAL1 P31 P32
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
P23 P22 P21 P20 VSS P02 P01 P00 P33
18-Pin DIP Configuration
18-Pin SOIC Configuration
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PRELIMINARY
Z86217/C17 CP95KEY1000
ABSOLUTE MAXIMUM RATINGS
Sym VDD TSTG TA Parameter Supply Voltage (*) Storage Temp Oper Ambient Temp Min -0.3 -65 Max +7 +150 Units V C C Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Notes: * Voltages on all pins with respect to GND See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load).
From Output Under T est
I
150 pF
Test Load Diagram
CAPACITANCE
TA = GND = 0V, f = 1.0 MHz, unmeasured pins to GND Parameter Input capacitance Output capacitance I/O capacitance Max 10 pF 20 pF 25 pF
Vdd SPECIFICATION
Vdd = 3.0V to 5.5V
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PRELIMINARY
Z86217/C17 CP95KEY1000
DC ELECTRICAL CHARACTERISTICS
TA = 0C to +70C Min Max 12 12 VDD + 0.3 VDD + 0.3 0.2 VDD 0.2 VDD VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD Typical @ 25C
Symbol Parameter Max Input Voltage VCH Clock Input High Voltage
VDD 3.0V 5.5V 3.0V 5.5V
Units V V V V V V V V V V V V V V V V V V V V V V A A A A
Conditions VIN = 250 A VIN = 250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
0.7 VDD 0.7 VDD VSS - 0.3 VSS - 0.3 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VDD - 0.4 VDD - 0.4
2.0 3.0 0.8 1.5 1.6 2.6 1.4 2.6 1.4 2.6 1.3 2.4 2.8 5.5 0.13 0.07 0.8 0.3 2.3
VCL
Clock Input Low Voltage
3.0V 5.5V
VIH VIH VIL VIL VOH VOL1 VOL2
Input High Voltage Schmitt-Triggered Input High Voltage CMOS Input Input Low Voltage Schmitt-Triggered Input Low Voltage CMOS Input Output High Voltge Output Low Voltage Output Low Voltage
3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
0.4 0.4 1.5 0.8 2.7
VLV VTP IIL IOL
VCC Low Voltage Protection Voltage Trip Point Voltage Input Leakage Output Leakage
IOH = -2.0 mA IOH = -2.0 mA IOL = +4.0 mA IOL = +4.0 mA IOL = 20.0 mA, 3 Pin Max IOL = 20.0 mA, 3 Pin Max @ 2 MHz Max
3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
0.4 VDD -1.0 -1.0 -1.0 -1.0 1.0 1.0 1.0 1.0
0.4 0.4
VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
Note: For 2.75V operating, the device operates down to VLV. The minimum operational VDD is determined on the value of the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases.
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PRELIMINARY
TA = 0C to +70C Min Max 1.5 3.0 2.0 4.0 3.0 6.0 0.6 1.3 0.8 1.5 1.0 2.0 200 200 Typical @ 25C 0.41 1.44 0.93 2.60 1.64 4.28 0.15 0.70 0.20 0.80 0.3 1.0 120 120
Z86217/C17 CP95KEY1000
Sym IDD
Parameter Supply Current
VDD 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Units mA mA mA mA mA mA mA mA mA mA mA mA A A
Conditions All Output and I/OPins Floating @ 1 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 4 MHz All Output and I/O Pins Floating @ 4 MHz HALT Mode VIN = 0V, VCC @ 1 MHz HALT Mode VIN = 0V, VCC @ 1 MHz HALT Mode VIN = 0V, VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 4 MHz HALT Mode VIN = 0V, VCC @ 4 MHz STOP Mode VIN = 0V, VCC WDT is Running STOP Mode VIN = 0V, VCC WDT is Running
IDD1
Standby Current
3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
IDD2
Standby Current
3.0V 5.5V
IPU
Pull-Up Current Port P20-P23 (100K) Port P24-P27* (20K) Port P00-P03 Port P31, P33
3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
-35 -100 -100 -400 -35 -100 80 250
-13 -57 -58 -270 -13 -56 40 160
A A A A A A A A
IPD
Pull-Down Current Port P32* (47K)
Note: *Available on the Z86C17 only.
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PRELIMINARY
Z86217/C17 CP95KEY1000
AC ELECTRICAL CHARACTERISTICS
TA = 0C to +70C 1 MHz 4 MHz Min Max Min Max 1,000 1,000 100,000 100,000 25 25 475 475 100 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 100 70 2.5TpC 2.5TpC 25 10 6 2 100 70 2.5TpC 2.5TpC 25 10 6 2 ms ms ms ms 2.5TpC 2.5TpC 4TpC 4TpC 100 100 ns ns ns ns 250 250 100,000 100,000 25 25 100 100 100 70
No Symbol 1 2 3 4 5 6 7 8 9 TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL TwIH
Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Timer Int. Request Input Low Time Int. Request Input High Time Watch-Dog Timer Time Out Timer Power-On Reset Time
VDD 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Units ns ns ns ns ns ns ns ns
Notes [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1,2] [1,2] [1] [1,2] [1] [1] [1] [1]
10 Twdt 11 TPOR
Notes: [1] Timing Reference uses 0.9 VDD for a logic 1 and 0.1 VDD for a logic 0. [2] Interrupt request through Port 3 (P33-P31)
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PRELIMINARY
Z86217/C17 CP95KEY1000
TIMING DIAGRAM
1 3
Clock
2 7 7 2 3
T
IN
4 6 5
IRQ
N
8 9
Electrical Timing Diagram
Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-con-
stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship.
formance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com
(c) 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
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